METHOD OF USING CLOCK CYCLE-TIME IN DETERMINING LOOP SCHEDULES DURING CIRCUIT DESIGN

摘要

A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations (201); receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determing existence of a placement clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification (206, 207).