| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce an area occupied by selection transistors which are arranged between a main bit line and sub-bit lines to reduce power consumption by reducing excess charges/discharges in a non-selected memory cell block in block erasure. <P>SOLUTION: A nonvolatile semiconductor storage device in which a memory cell array is formed over a plurality of well-areas 3a, 3b, is provided with the main bit line 14 arranged in common to each of the plurality of well-areas, the sub-bit lines 13a, 13b arranged for each of the plurality of well-areas and connected to the memory cell, and a selection transistor BTRB for selectively connecting sub-bit lines to the main bit line. When erasing the memory cell, 1st voltage is applied to a well-area to which the memory cell to be erased belongs, and 2nd voltage is applied to the gate electrode of the selection transistor. The 2nd voltage is of the same polarity as the 1st voltage, and is equal to or higher than a threshold voltage of the selection transistor and lower than the 1st voltage. <P>COPYRIGHT: (C)2004,JPO</p> |
