发明名称 |
Method for fabricating laminated silicon gate electrode |
摘要 |
Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
|
申请公布号 |
US2004077155(A1) |
申请公布日期 |
2004.04.22 |
申请号 |
US20020274570 |
申请日期 |
2002.10.21 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHEN CHIA-LIN;YAO LIANG-GI;CHEN SHIH-CHANG |
分类号 |
H01L21/20;H01L21/28;H01L21/30;H01L29/49;H01L29/78;(IPC1-7):H01L21/20;H01L21/36 |
主分类号 |
H01L21/20 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|