METHOD FOR SEMICONDUCTOR GATE LINE DIMENSION REDUCTION

摘要

To reduce the width of a MOSFET gate, the gate (16) is formed with a hardmask (14) formed thereupon. An isotropic etch is then performed to trim the gate (16) in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.