发明名称 PACKET PROCESSING APPARATUS AND METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To realize reduction in the scale of hardware and cost-down thereof with respect to buffering of received packets and the storage of analysis data for the received packets. <P>SOLUTION: The packet processing apparatus for temporarily storing externally received packets and analyzing the stored packets includes: a memory 3b having packet areas P1, P2 for storing the externally received packets and an analysis area PA for storing the analysis data for the packets; and a memory control section 3d for writing the packets or the packet analysis data to the packet areas P1, P2 or the analysis area PA in time division and reading the packets or the packet analysis data from the packet areas P1, P2 or the analysis area PA in time division. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004128748(A) 申请公布日期 2004.04.22
申请号 JP20020287937 申请日期 2002.09.30
申请人 ANDO ELECTRIC CO LTD 发明人 TATSUMI KANJI
分类号 H04L12/70;H04L12/66;H04L29/06;(IPC1-7):H04L12/56 主分类号 H04L12/70
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