| 摘要 |
PROBLEM TO BE SOLVED: To enhance the performance of a system where a plurality of master modules are connected to a plurality of slave modules by a bus. SOLUTION: The bus Ybus has a switch SW with a plurality of master boards and a plurality of slave boards. The plurality of master boards can be connected to some of the plurality of slave boards. In the bus, an address phase for issuing addresses and commands is separated from a data phase for issuing write data. Before the data phase ends, the address phase of the next transaction can be issued. COPYRIGHT: (C)2004,JPO
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