On-chip PLL locked frequency determination method and system

摘要

In some embodiments, the present application describes an on-chip system and method of determining the effective locked frequency of a PLL. The locked frequency of the PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determined whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal match the jitter in the locked frequency of the PLL, the respective delay of the test signal is used to determine the effective locked frequency of the PLL.