| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a deskew circuit which corrects skew between a clock and data and between various data of a data bus in data transfer which transfers mass data at high speed between packages and transfers the clock and the data in parallel. <P>SOLUTION: A variable delay circuit is provided between a receiver which receives the data and a flip-flop which latches the data first by every bit of each of the clock and the data. A detection pattern for detecting the stable region of reception data is repeatedly transmitted before performing the data transfer, the delay value of the variable delay circuit is calculated so that the starting point and end point of the data match the rising edge of the clock, and the delay circuit is set to a delay value at which transfer data are stably received. <P>COPYRIGHT: (C)2004,JPO</p> |
