METHOD FOR FABRICATING TRANSISTOR WITH PUNCHTHROUGH PREVENTING REGION

摘要

PURPOSE: A method for fabricating a transistor with a punchthrough preventing region is provided to form a punchthrough preventing region self-aligned with a common gate electrode of NMOS and PMOS transistors under the common gate electrode by forming the first insulation layer for defining a gate electrode region and by performing a patterning process only once. CONSTITUTION: A P-well region(1) and an N-well region(10) are formed in the surface of a semiconductor substrate. An isolation layer(16) for defining an active region in the P-well and N-well regions is formed on a predetermined region of the resultant structure. The first insulation layer pattern(16) crosses the active regions defined in the P-well and N-well regions, having a groove with a predetermined width. The groove on the N-well region is covered with the second insulation layer pattern. The first punchthrough preventing region having a higher density than that of the P-well region is selectively formed under the surface of the active region exposed by the groove on the P-well region. The groove on the P-well region is filled with the first gate electrode(24). The second insulation layer pattern is removed to expose the groove on the N-well region. The second punchthrough preventing region(26) having a higher density than that of the N-well region is formed under the surface of the active region exposed by the groove on the N-well region. The groove on the N-well region is filled with the second gate electrode(30).