发明名称 |
Semiconductor device used in two systems having different power supply voltages |
摘要 |
A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively. |
申请公布号 |
US6724223(B2) |
申请公布日期 |
2004.04.20 |
申请号 |
US20020287643 |
申请日期 |
2002.11.05 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
ICHIGUCHI TETSUICHIRO;NAGASAWA TSUTOMU;YAMAUCHI TADAAKI;TIAN ZENGCHENG;SUWA MAKOTO;MATSUMOTO JUNKO;OKAMOTO TAKEO;YONETANI HIDEKI |
分类号 |
H01L21/822;G11C5/14;G11C7/22;G11C11/407;G11C11/4074;G11C11/4076;G11C11/409;H01L21/8242;H01L27/02;H01L27/04;H01L27/108;H03K19/0175;(IPC1-7):H03K19/017 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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