发明名称 Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains
摘要 Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.
申请公布号 US6725388(B1) 申请公布日期 2004.04.20
申请号 US20000592670 申请日期 2000.06.13
申请人 INTEL CORPORATION 发明人 SUSNOW DEAN S.
分类号 G06F5/10;H04L7/02;H04L7/10;(IPC1-7):G06F1/12 主分类号 G06F5/10
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