Memory cell using negative differential resistance field effect transistors

摘要

A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.