Decoding circuit using path sequence including feed-back type path sequence storing blocks

摘要

A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68. A storing element block output circuit 64 and storing element block output terminals 65(1) to 65(D) are provided in each of the storing element blocks 60(1) to 60(D) so that a path memory circuit output 67 may be outputted through an OR circuit 66.