发明名称 A CONDUCTIVE CHANNEL PSEUDO BLOCK PROCESS AND CIRCUIT TO INHIBIT REVERSE ENGINEERING
摘要 <p>A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.</p>
申请公布号 AU2003278917(A1) 申请公布日期 2004.04.19
申请号 AU20030278917 申请日期 2003.09.23
申请人 HRL LABORATORIES, LLC 发明人 LAP-WAI CHOW;WILLIAM, M. , JR. CLARK;GAVIN, J. HARBISON;JAMES, P. BAUKUS
分类号 G06K19/073;H01L23/58;(IPC1-7):H01L23/58;G11C7/24;H01L21/285 主分类号 G06K19/073
代理机构 代理人
主权项
地址