| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption and to accelerate processing operations by using a memory such as a general RAM for a path metric storage part and a path select signal storage part, and by decreasing the number of times of memory access in ACS arithmetic and trace-back arithmetic in a viterbi decoder. SOLUTION: A trace-back arithmetic part 107 for outputting decoded data by searching status transitions in the past while using path select signals in the past read out of a path select signal storage part 106 is provided with a shift register 304 for storing a viterbi state according to a surviving path based upon a path select signal obtained from the path select signal storage part 106, and a viterbi state prediction part 305 for predicting a part of a viterbi state to be next updated. COPYRIGHT: (C)2004,JPO
|
