发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD
摘要 <P>PROBLEM TO BE SOLVED: To perform a scan test without lowering security. <P>SOLUTION: This circuit is constituted so that a flip-flop constituting a scan chain is reset when the scan test is started or finished by an edge of a mode signal for switching between an ordinary operation and the scan test. An internal storage means can not be accessed at the scan test time. A dummy flip-flop operating only at the scan test time is connected to the scan chain, and shift-out by the scan chain can not be performed at the ordinary operation time. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004117029(A) 申请公布日期 2004.04.15
申请号 JP20020277285 申请日期 2002.09.24
申请人 SONY CORP 发明人 KAYUKAWA YOSHITAKA;AOKI TETSUYA;HAMAGUCHI TAKAHIRO;OSHIMA NORIYUKI
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22;H01L21/66 主分类号 G01R31/28
代理机构 代理人
主权项
地址