发明名称 |
High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system |
摘要 |
A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
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申请公布号 |
US2004073909(A1) |
申请公布日期 |
2004.04.15 |
申请号 |
US20020268729 |
申请日期 |
2002.10.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARIMILLI RAVI KUMAR;WILLIAMS DEREK EDWARD |
分类号 |
G06F9/00;G06F9/46;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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