Delay locked loop circuit for memory device, has delay line unit with cells, delaying external clock signal, and selecting output signals of delay cells based on control signals from two control circuits

摘要

The circuit (30) has a phase detector (31) sensing a phase difference between an external clock signal and a feed back internal clock signal, and generating up-signals and down-signals corresponding to the phase difference. A delay line unit (34) with cells, delays the external clock signals through the delay cells, and selects output signals of the delay cells based on control signals from two control circuits (32,33). One control circuit, in response to up and down-signals, generates a control signal course locking the phase difference between the external clock signal and the feed back internal clock signal and another control signal fine locking the phase difference. Another control circuit, in response to the up-signals and the down-signals, generates third and fourth control signal performing coarse duty and fine duty error correction of the external clock signals, respectively. An independent claim is also included for a method of correcting a clock signal duty cycle in a delay locked loop circuit having a delay line unit that includes delay cells connected in series.