| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To remove an effect of clock latency non-deterministically generated when an output signal of an integrated electronic circuit is tested. <P>SOLUTION: A DUT output signal is processed by a filter using information about a time location possibly generating the non-deterministic latency. The non-deterministic latency is removed before a bitstream is evaluated by a comparison with an expected bitstream. The signal whose latency is removed, is evaluated by the comparison with the predetermined and expected bitstream. <P>COPYRIGHT: (C)2004,JPO</p> |
