发明名称 |
Pipelining cache-coherence operations in a shared-memory multiprocessing system |
摘要 |
One embodiment of the present invention provides a system that facilitates pipelining cache coherence operations in a shared memory multiprocessor system. During operation, the system receives a command to perform a memory operation from a processor in the shared memory multiprocessor system. This command is received at a bridge that is coupled to the local caches of the processors in the shared memory multiprocessor system. If the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, the system delays the command until the in-progress pipelined cache coherency operation completes. Otherwise, the system reflects the command to local caches of other processors in the shared memory multiprocessor system. The system then accumulates snoop responses from the local caches of the other processor and sends the accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system.
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申请公布号 |
US2004073623(A1) |
申请公布日期 |
2004.04.15 |
申请号 |
US20020256610 |
申请日期 |
2002.09.27 |
申请人 |
BENKUAL JACK;ATHAS WILLIAM C.;BRATT JOSEPH P.;HOCHSPRUNG RONALD RAY |
发明人 |
BENKUAL JACK;ATHAS WILLIAM C.;BRATT JOSEPH P.;HOCHSPRUNG RONALD RAY |
分类号 |
G06F12/08;G06F13/00;G06F15/167;(IPC1-7):G06F15/167 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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