| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock converter for outputting a clock signal with a frequency higher than that of an input signal by phase-locking the input signal with a PLL feedback signal extracted from a voltage-controlled oscillation means. <P>SOLUTION: The voltage-controlled oscillation means 4 in the clock converter outputs a noninverting feedback signal for a positive feedback loop from one output terminal of a buffer means 13 configuring part of the positive feedback loop employing a voltage-controlled phase shift means 14 and outputs the PLL feedback signal from the other output terminal. The PLL feedback signal is fed back to a phase comparison means 2 via a signal transmission circuit 5. As a result, the PLL feedback loop not affected by a load can be formed and a stable high frequency clock signal is outputted. Further, employing a thin wiring pattern of the signal transmission circuit 5 can realize the downsized clock converter 1. <P>COPYRIGHT: (C)2004,JPO |
