发明名称 |
Electrostatic discharge protection device for mixed voltage interface |
摘要 |
An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
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申请公布号 |
US2004070900(A1) |
申请公布日期 |
2004.04.15 |
申请号 |
US20020268756 |
申请日期 |
2002.10.11 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
KER MING-DOU;HSU KUO-CHUN;JIANG HSIN-CHIN |
分类号 |
H01L27/02;H02H9/00;(IPC1-7):H02H9/00 |
主分类号 |
H01L27/02 |
代理机构 |
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主权项 |
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地址 |
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