| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide the technology to reduce electrical resistance between a contact plug and an impurity region connected electrically to such a plug while insulation property is maintained between a gate electrode and the contact plug. <P>SOLUTION: A side wall insulation film 17 is formed at the side surface of a gate structure 60 provided on a semiconductor substrate 1, and the epitaxial layers 19a, 19b are formed on the self-alignment basis on the n-type impurity regions 13a, 13b to provide the side wall insulation film 17 against the gate electrode 50. An etching rejection film 20 and an interlayer insulation film 21 are formed in this sequence on the entire part. The interlayer insulation film 21 is etched using the etching rejection film 20 as an etching stopper, and the exposed etching rejection film 20 is then etched. Accordingly, the contact holes 30a, 30b are formed to reach the epitaxial layers 19a, 19b. <P>COPYRIGHT: (C)2004,JPO |
