发明名称 APPARATUS AND METHOD FOR CONTROLLING DISPLAY OF SEMICONDUCTOR MEMORY FAIL
摘要 PROBLEM TO BE SOLVED: To superpose detailed fail data on a reduced fail display and display them at a high speed by extracting reduced fail data from a fail compression device provided for a semiconductor device, performing a reduced display by a fail display control apparatus, then extracting and analyzing non-reduced fail data on a part instructed by an operator from a fail memory in a fail semiconductor testing device. SOLUTION: This control apparatus 3 performs control in such a way that the results of testing and result of analysis of the semiconductor testing device 4 are displayed on a display device 1. The control apparatus 3 includes a display control means 31 for displaying the reduced fail data stored in a reduced fail storage 32 on the display device, an instruction means 2 for instructing any part of the reduced fail data displayed on the display device, a fail analysis means 33 for retrieving the fail data of the part instructed by the instruction means from the fail memory 41 in the semiconductor testing device, and a fail analysis result display means 31 for superposing the results of analysis of the fail analysis means on reduced fail information displayed on the display device and displaying them. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004117056(A) 申请公布日期 2004.04.15
申请号 JP20020277812 申请日期 2002.09.24
申请人 ANDO ELECTRIC CO LTD 发明人 KAMIYA HIROTOSHI
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
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