发明名称 Method and apparatus for gigabit packet assignment for multithreaded packet processing
摘要 A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads-one for header segment processing and the other for handling payload segment(s)-or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.
申请公布号 US2004071152(A1) 申请公布日期 2004.04.15
申请号 US20030684078 申请日期 2003.10.10
申请人 INTEL CORP 发明人 WOLRICH GILBERT;BERNSTEIN DEBRA;ADILETTA MATTHEW J;HOOPER DONALD F
分类号 H04L12/56;(IPC1-7):H04L12/28 主分类号 H04L12/56
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