A semiconductor die package (100) including a semiconductor die (108) comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip (101) having a major surface (101(a)) is electrically coupled to the drain region. A gate lead (112) is electrically coupled to the gate region. A source lead (111) is ectrically coupled to the source region. A non-conductive molding material (102) encapsulates the semiconductor die (108). The major surface (101(a)) of the drain clip (101) is exposed through the non-conductive molding material (102).
申请公布号
WO2004032232(A1)
申请公布日期
2004.04.15
申请号
WO2003US29142
申请日期
2003.09.17
申请人
FAIRCHILD SEMICONDUCTOR CORPORATION;MADRID, RUBEN;QUINONES, MARIA, CLEMENS, Y.