发明名称 METHOD OF ARRANGING MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a method of arranging memory cells which can stabilize operations, during reading and during writing. <P>SOLUTION: After a first memory cell array 13 is formed by a first cell unit 12, a second memory cell array 15 is formed by a second cell unit 14 separated from a non-adjoining region 17, to be provided along the bit-line direction for arrangement of a back-gate in a memory cell array 11 of a semiconductor memory device. As a result of this, the front and rear memory cells separated from the non-adjoining region 17 are not reversed with each other. The number of bit line contacts to be provided to mutual bit lines to be made as the pair respectively (a bit line BLA and an X bit line XBLA, a bit line BLB and an X bit line XBLB) mutually become nearly equal. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004119946(A) 申请公布日期 2004.04.15
申请号 JP20020285245 申请日期 2002.09.30
申请人 FUJITSU LTD 发明人 KASUGA KENJI
分类号 G11C11/41;G11C7/06;G11C7/18;H01L21/8242;H01L21/8244;H01L27/02;H01L27/10;H01L27/108;H01L27/11 主分类号 G11C11/41
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