发明名称 DESIGNING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To enhance the utilizing efficiency of a chip area while preventing the occurrence of latchup in the case of designing a semiconductor device by the standard cell system. SOLUTION: Input output cells are configured into core parts 201, 203 configuring transistors, a guard band, and space parts 202, 204. A plurality of the input output cell core parts 201, 203 are placed adjacent to each other. Whether or not a problem of latchup takes place in the combination of the input output cell core parts 201, 203 adjacent to each other is discriminated. When there is any problem, cells configuring the guard band and the space parts 202, 204 proper to the respective input output cell core parts 201, 203 are provided between the input output cell core parts 201, 203 adjacent to each other, and when there is no problem, no cells configuring the guard band and the space parts 202, 204 proper to the respective input output cell core parts 201, 203 are provided between the input output cell core parts 201, 203 adjacent to each other. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004119744(A) 申请公布日期 2004.04.15
申请号 JP20020282077 申请日期 2002.09.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRATA TATSUYA
分类号 G06F17/50;H01L21/82;H01L21/822;H01L21/8238;H01L27/04;H01L27/092;(IPC1-7):H01L21/82;H01L21/823 主分类号 G06F17/50
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