Phase detector having improved timing margins

摘要

Phase detector (10; 60) constructed from a plurality of multi-input gates (115, 116, 117, 118; 615, 616, 617, 618) which combine combinations of unretimed input data (102, 103; 602, 603) with retimed data (104; 604) and with clock signals (105; 605) to achieve output pulses proportional to the phase difference between the unretimed data and the clock. In the embodiment the phase detector comprises an input (101; 601) for receiving data signals; an input (100; 600) for receiving clock signals; an output (110; 610) for providing phase control signals; data retiming circuitry (111, 112; 611, 612) for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom; a plurality of multi-input gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit; and a combiner (121; 619) for mixing the outputs of at least two of said gates.