| 摘要 |
A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.
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