发明名称 |
One sample per symbol high rate programmable parallel architecture for digital demodulation |
摘要 |
A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.
|
申请公布号 |
US6721371(B1) |
申请公布日期 |
2004.04.13 |
申请号 |
US20000477882 |
申请日期 |
2000.01.05 |
申请人 |
L-3 COMMUNICATIONS CORPORATION |
发明人 |
BARHAM STEVEN T;BAGLEY ZACHARY C;HORNE LYMAN D |
分类号 |
H03H17/02;H04L25/03;(IPC1-7):H04L27/22 |
主分类号 |
H03H17/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|