发明名称 |
Dual-edge-correcting clock synchronization circuit |
摘要 |
A clock distribution circuit and method in which the incoming clock frequency is divided by two to create a reduced-frequency global clock signal. A dual-edge-correcting clock synchronization circuit aligns both the rising and falling edges of the global clock signal to separately to nullify the clock-distribution errors associated with rising and falling clock edges.
|
申请公布号 |
US6720810(B1) |
申请公布日期 |
2004.04.13 |
申请号 |
US20020173212 |
申请日期 |
2002.06.14 |
申请人 |
XILINX, INC. |
发明人 |
NEW BERNARD J. |
分类号 |
G06F1/12;H03K5/13;H03K5/135;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|