| 摘要 |
A system having multiple encoders of different maximum error correction capability, which reduces the entire size of the system by allowing most of the system to be shared among these encoders. This is accomplished by using an encoder that is capable of calculating parities of 2 or more kinds of bit numbers with different error correction capability. The system includes a circuit that generates a modified word by assigning a predetermined value to input an information word; and a circuit that generates an intermediate signal "u" by a linear operation using a modified word and matrix "P". These circuits are combined with linear operation circuits for generating value of parity p1, . . . , palpha, each of whose bit number is different, by a linear operation using all or part of the intermediate signal and matrixes Q1, . . . , Qalpha respectively.
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