| 摘要 |
In semiconductor integrated circuit devices containing a macro, a skew occurs between the clock pulse supplied to the latch in that mother circuit and the clock pulse supplied to the latch inside the macro. These clock skews obstruct the high frequency operation of the semiconductor integrated circuit device clock frequency so the semiconductor integrated circuit device cannot be operated at high speed. In a semiconductor integrated circuit device having a first clock processor means to generate a third clock pulse so a first clock pulse and a second clock pulse are input at an identical phase and identical frequency, a second clock processor means to generate a fifth clock pulse so that a third and a fourth clock pulse are input at an identical phase and identical frequency, and a first latch group and a second latch group comprised of a plurality of latches, and in this semiconductor integrated circuit device the second clock pulse is generated by way of a buffer or a divider from a third clock pulse, a fourth clock pulse is generated by way of a buffer or a divider from a fifth clock pulse, and the third clock pulse is supplied to the first latch group by way of a buffer and the fifth clock pulse is supplied to the second latch group by way of a buffer.
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