发明名称 |
BURST-MODE CLOCK SIGNAL REGENERATING APPARATUS AND METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a burst-mode clock signal regenerating apparatus and method. <P>SOLUTION: A first delay apparatus outputs input data by delaying it for half the period of the input data. An XOR gate performs an XOR operation of the input data and an output signal of the first delay apparatus and outputs result of the operation. An OR gate outputs a regenerated clock signal by an OR operation of a signal output from the XOR gate and a second delay signal. A second delay apparatus delays the output signal of the OR gate for integral multiple of period of the input data, and supplies it to the OR gate. As a result, frequency of the regenerated clock signal is not affected by the time delays caused via the gate, even if the phase of the input data is changed for each packet. <P>COPYRIGHT: (C)2004,JPO |
申请公布号 |
JP2004112754(A) |
申请公布日期 |
2004.04.08 |
申请号 |
JP20030145476 |
申请日期 |
2003.05.22 |
申请人 |
KOREA ELECTRONICS TELECOMMUN |
发明人 |
CHOI JEE-YON;HA HONG HYUN;KIM HAE GEUN;I JONHYUN |
分类号 |
H04L7/02;H03K5/135;H04L7/027 |
主分类号 |
H04L7/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|