发明名称 DELAY TIME CALCULATING DEVICE AND INTEGRATED CIRCUIT DESIGN DEVICE
摘要 PROBLEM TO BE SOLVED: To obtain a delay time calculating device and an integrated circuit design device capable of exactly calculating the delay time of a gate. SOLUTION: The delay time calculating device is provided with a resistance capacity specification part 25 which specifies source resistance and diffusion capacity before process fluctuation at the gate as an object of delay time calculation and specifies the wiring resistance and wiring capacity of wiring connected with the gate after the process fluctuation and calculates the delay time of the gate on the basis of the specification contents by the resistance capacity specification part 25. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004110701(A) 申请公布日期 2004.04.08
申请号 JP20020275543 申请日期 2002.09.20
申请人 RENESAS TECHNOLOGY CORP 发明人 SAKANO YOSHIO
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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