INTEGRATED CIRCUIT WITH CLOCK SIGNAL DUTY CYCLE CONTROL

摘要

An integrated circuit (100) has a clock signal distribution network (140) for distributing a parent clock pulse signal that is provided through a conductor (102). At the inputs, the clock distribution network (140) is coupled to a clock signal modifying circuit (120) and on the outputs the clock distribution network (140) is coupled to a reference generating circuit (160). The reference generating circuit (160) is arranged to provide the clock signal modifying circuit (120) with a direct current voltage that is proportional to the duty cycle of the clock pulse signal that is distributed through the clock distribution network (140). The clock signal modifying circuit (120) is arranged to alter the duty cycle of the incoming parent clock pulse signal responsive to the direct current voltage. The arrangement implements a feedback mechanism for reducing deviations from a 50% duty cycle of a clock pulse signal distributed through the clock distribution network (140).