METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To facilitate layout verification of a circuit in which an analog circuit and a digital circuit coexists. SOLUTION: Wiring as a possible noise source and wiring which is not noise-resistant are specified on a circuit diagram are indicated on a circuit, and an identification display means 11 identifies a pair of wiring patterns the parasitic capacity of which exceeds a specific value and displays it on the circuit diagram and a layout diagram when the parasitic capacity between the wiring patterns as the possible noise source and the wiring which is not noise-resistant is extracted. COPYRIGHT: (C)2004,JPO