AN INTERCONNECT-AWARE METHODOLOGY FOR INTEGRATED CIRCUIT DESIGN
摘要
An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.
申请公布号
WO03075189(A3)
申请公布日期
2004.04.08
申请号
WO2003IB00819
申请日期
2003.03.04
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM (SCHWEIZ);ALON, AMIR;GOREN, DAVID;GORDIN, RACHEL;LIVSHITZ, BETTY;SHERMAN, ANATOLY;ZELIKSON, MICHAEL
发明人
ALON, AMIR;GOREN, DAVID;GORDIN, RACHEL;LIVSHITZ, BETTY;SHERMAN, ANATOLY;ZELIKSON, MICHAEL