发明名称 |
CLOCK POWER REDUCTION TECHNIQUE USING MULTILEVEL VOLTAGE INPUT CLOCK DRIVER |
摘要 |
A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced. |
申请公布号 |
WO03102750(A3) |
申请公布日期 |
2004.04.08 |
申请号 |
WO2003US14679 |
申请日期 |
2003.05.12 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
TRIVEDI, PRADEEP, R.;BOBBA, SUDHAKAR |
分类号 |
G06F1/10;G06F1/32 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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