| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a circuit unit compact with a small occupied area and capable of transferring data by making a clock trigger adjustment even when a plurality of wiring is influenced by skew caused by the difference in the number of loads and wiring length, and transmitting data at high speed between ICs even when the wiring length is dispersed. <P>SOLUTION: The IC having a terminal which inputs two kinds of clock triggers is used. Although skew occurs between signals when load and wiring length per one network differ, clock with different phases is inputted to nullify the skew. The skew is thereby eased by the clock of different timing even in bus wiring with the skew to allow high speed transmission without an error to all bits. <P>COPYRIGHT: (C)2004,JPO</p> |
