Memory array apparatus with reduced data accessing time and method for the same

摘要

A memory array apparatus with shorter data accessing time is proposed. The memory array apparatus comprises a register administrator and a plurality of data registers between a micro controller and at least one memory array. The data to be accessed are divided into a plurality of data blocks according to a predetermined data unit. The data block is firstly stored in corresponding data register and then read by the main frame or stored into the corresponding memory array. At the same time, the next data block is stored in the corresponding data register through circuit switched by the micro controller. The pending time of the main frame and the data accessing time can be advantageously reduced.