发明名称 |
Method and apparatus for implementing a data processor adapted for turbo decoding |
摘要 |
An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.
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申请公布号 |
US6718504(B1) |
申请公布日期 |
2004.04.06 |
申请号 |
US20020165146 |
申请日期 |
2002.06.05 |
申请人 |
ARC INTERNATIONAL;ALCATEL |
发明人 |
COOMBS ROBERT;TALBOT JONATHAN;WORM ALEXANDER |
分类号 |
H03M13/00;H03M13/03;H03M13/29;H03M13/39;H03M13/45;(IPC1-7):H03M13/29 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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