发明名称 Systems and methods for prefetch operations to reduce latency associated with memory access
摘要 A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.
申请公布号 US6718454(B1) 申请公布日期 2004.04.06
申请号 US20000563060 申请日期 2000.04.29
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 EBNER SHARON M.;WICKERAAD JOHN A.
分类号 G06F12/00;G06F12/02;G06F12/08;G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F12/00
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