| 摘要 |
1,179,274. Data processing ; division HONEYWELL Inc. 10 Feb., 1967 [28 Feb., 1966], No. 6620/67. Heading G4A. A pair of multidigit operands are justified before arithmetic operations are performed thereon by alternately scanning the operands digit-by-digit and from opposite ends until indications of the highest order digit of that one of the operands which is scanned from the low order end is detected. In a character processor having an arithmetic unit operating serially by character on variable length operands, before a division operation by the over-and-over subtraction technique is started the divisor and dividend operands are scanned alternately character-by-character to establish their lengths so that unnecessary initial subtractions are avoided. As described, a divide instruction comprises a function code field, an A or divisor address field and a B or dividend address field. Each stored character comprises 9 bits, four bits storing digital information in BCD or binary form, two zone bits used in the units position of an operand for indicating its sign, two punctuation bits used as a word mark to indicate the high order end of an operand and one parity bit. The A address of the divide instruction indicates the units position of the divisor whereas the B address indicates the high order end of the dividend. In the performance of the divide instruction the operand digits are initially scanned alternately by respectively decrementing and incrementing A and B address counters until either the word mark of the A operand or. the sign bits of the B operand are detected. If the sign bits of the B operand are detected first, indicating a fractional quotient, the instruction is terminated after determining the sign of the quotient. If the word mark of the A operand is detected first a reverse scan with corresponding counter modifications may be initiated to check for insignificant zeros and then the division operation proper is started with the operands so aligned that a useful subtraction is achieved immediately. Subtraction is parallel within decimal digit. When a change of sign in the partial remainder is detected the divisor is added back and subtractions continued with the operands in shifted relationship. Also when a change of sign is detected, a temporary register tallying the number of successful subtractions is transferred to the quotient area which is provided adjacent to the high-order end of the dividend and may, if necessary, extend into the original dividend area as this contracts. Three working areas for storing reference addresses associated with the divisor, dividend and quotient, respectively, as well as two counters for sequentially accessing the characters of the divisor and dividend are provided. The operands and instructions may be stored in a magnetic core store. A control memory comprising sixteen 15-bit registers is provided for programme sequencing and other functions. |
