| 摘要 |
PROBLEM TO BE SOLVED: To provide an input buffer circuit with a constant reaction rate in output inversion, regardless of a potential level where complementary signals cross. SOLUTION: Input buffer circuits 20 and 30, which are the input buffer circuits of current mirror type, are combined. The output signal OUT is outputted through an inverter 40 by synthesizing the waveforms of the both output signals OUT1 and OUT2 in the waveform on a node N4. The output signals OUT1 and OUT2 are synthesized in the waveforms at the same phase by inputting complementary clock signals CK and /CK from the opposite direction, even though the clock signals CK and /CK are opposite in phase. COPYRIGHT: (C)2004,JPO |
