BIT LINE SENSE AMPLIFIER DRIVE CONTROL CIRCUIT AND METHOD OF SYNCHRONOUS DRAM FOR SELECTIVELY SUPPLYING OPERATING VOLTAGE AND TEMPORARILY INTERRUPTING SUPPLY

摘要

PROBLEM TO BE SOLVED: To provide a bit line sense amplifier drive control circuit and a bit line sense amplifier drive control method of a synchronous DRAM, that enable effective data output, even in a short clock period by reducing time required for the primary amplification of data. SOLUTION: An operating voltage in a bit line sense amplifier is selectively supplied and is temporarily interrupted. More specifically, the synchronous DRAM includes: a memory array containing at least first and second column blocks being divided by a column address; the first bit line sense amplifier being composed so that data outputted from the first column block of the memory cell array are sensed; and a second bit line sense amplifier being composed so that data outputted from the second column block are sensed. The bit line sense amplifier drive control circuit or the bit line sense amplifier drive control method supplies the operating voltage to the first and second bit line sense amplifiers, by responding to a row address selection signal and temporarily interrupts the supply of the operating voltage to the second bit line sense amplifier, by responding to a column selection signal for selecting the column address of the first column block. COPYRIGHT: (C)2004,JPO