发明名称 WAFER FOR EVALUATING PACKAGE OF SEMI-CONDUCTOR CIRCUIT, AND CHIP EVALUATION DEVICE USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a test chip for evaluating packages of different sizes out of a semi-conductor wafer of one kind. SOLUTION: Adjacent wire bonding pads 22A1, 22A2, etc. inside and outside single chips 21A, 21B, etc. are connected to each other to constitute a daisy chain on a semi-conductor wafer 20. Single chips facing each other diagonally and the wire bonding pads are connected to each other to constitute the daisy chain, and test chips 25 of substantially same size and shape as those of chips used for mass production are cut out of the semi-conductor wafer 20. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004101223(A) 申请公布日期 2004.04.02
申请号 JP20020259817 申请日期 2002.09.05
申请人 SANYO ELECTRIC CO LTD 发明人 TAMURA HIROYUKI
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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