| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide non-volatile memories which permit integration to a higher scale even if scaling of peripheral transistors is difficult. <P>SOLUTION: A flash memory having hierarchical bit line configuration is provided with column reset/bit line test transistor regions 4a commonly to a plurality of cell blocks 3a sharing upper layer bit lines MBL0, MBL1, etc., so that data lines DL connected with sense amplifiers can be selectively disconnected from the upper layer bit lines. <P>COPYRIGHT: (C)2004,JPO</p> |
