发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT DESIGN APPARATUS
摘要 PROBLEM TO BE SOLVED: To automatically generate a layout which can arrange a circuit composed of a plurality of transistors in a narrow-width region. SOLUTION: A searching means 221 searches for a group in which one or more routes passing through the same transistor are collected by inputting the data of the circuit and which can cover a circuit network by combining routes of the same group. An extracting means 222 extracts the group having the minimum route numbers among the searched route groups. A width determining means 223 determines a layout width based on the widths of the source electrode and drain electrode of each transistor, the width of a region between the source electrode and the drain electrode, the width of a region between source electrodes or drain electrodes which are not shared in adjoining transistors, the number of the transistors, and the minimum route number. A layout determining means 224 generates layout information in which all the source electrodes, drain electrodes and gate electrodes of the transistors included in the circuit are arranged in parallel each other in the narrow-width region having the determined width. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004103890(A) 申请公布日期 2004.04.02
申请号 JP20020265067 申请日期 2002.09.11
申请人 NEC CORP 发明人 NONAKA YOSHIHIRO
分类号 G06F17/50;H01L21/77;H01L21/82;H01L21/822;H01L21/84;H01L23/528;H01L27/02;H01L27/04;H01L27/12;(IPC1-7):H01L21/822 主分类号 G06F17/50
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